index - Equipe Secure and Safe Hardware Accéder directement au contenu

 

Dernières publications

Mots clés

Side-Channel Attacks Resistance AES ASIC Active shield Randomness Simulation RSA Receivers Side-Channel Analysis Mutual Information Analysis MIA Neural networks Sensors Fault injection attack Temperature sensors Protocols PUF Image processing Dual-rail with Precharge Logic DPL Side-channel attacks Information leakage Formal methods Differential Power Analysis DPA Power-constant logic Side-channel attacks SCA Reliability Signal processing algorithms Voltage Variance-based Power Attack VPA Tunneling magnetoresistance Application-specific VLSI designs Training TRNG Aging Side-channel analysis SCA FPGA Sécurité Energy consumption Writing Reverse engineering Electromagnetic Field programmable gate arrays Field Programmable Gates Array FPGA Magnetic tunnel junction CPA Fault injection Hardware security Spin transfer torque STT-MRAM Masking MRAM Security Computational modeling Authentication Masking countermeasure Estimation Formal proof Cryptography Power demand Reverse-engineering Convolution Countermeasure Dynamic range CRT Random access memory DRAM Linearity Machine learning Routing FDSOI Process variation SoC Robustness Steadiness Side-Channel Analysis SCA Asynchronous Countermeasures Internet of Things Intrusion detection 3G mobile communication Logic gates Confusion coefficient Magnetic tunneling Security and privacy Security services Costs Switches Elliptic curve cryptography Transistors Filtering OCaml Differential power analysis DPA Lightweight cryptography GSM Circuit faults Defect modeling Hardware Loop PUF Side-channel attack

 

Documents avec texte intégral

210

Références bibliographiques

427

Open access

39 %

Collaborations